library verilog;
use verilog.vl_types.all;
entity mod_divide is
    generic(
        dw_p            : integer := 16
    );
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        req             : in     vl_logic;
        numer           : in     vl_logic_vector;
        denom           : in     vl_logic_vector;
        quotient        : out    vl_logic_vector;
        remain          : out    vl_logic_vector;
        valid           : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of dw_p : constant is 2;
end mod_divide;
